1. Field of the Invention
The present invention generally relates to integrated circuits and more particularly to minimizing path delay variations in integrated circuits.
2. Background Description
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition and etc.
Mask shapes each may be grouped into one of four types: line/space arrays, isolated lines, isolated spaces, and contact holes. Ideally, fabrication parameters such as process biases applied to features on a particular layer affects all types of features uniformly on that layer. Unfortunately, all feature types do not respond uniformly. In particular, isolated lines and minimum pitch line/space arrays known as contact pitch lines behave differently to focus. Contacted pitch lines are minimum pitch line/space arrays on a particular layer in the minimum line width and spacing plus additions for via or contact covers or landing pads. When printed out-of-focus, contact pitch lines get wider (and spaces shrink), while isolated lines get narrower. This dichotomy has become especially troublesome as image dimensions have shrunk.
Since, typically, devices are much wider than they are long, the typical device has a short gate (and corresponding channel), i.e., the minimum shape dimension. Device current is inversely proportional to device length. Device performance is inversely related to device current (lower current means longer delays) and power is related to the square of device current. To densely pack a circuit such as a two bit adder or other complicated logic function, contact pitch lines are formed over silicon islands with device widths being in the direction of the length and device lengths being the line width. A multiplier built from such two bit adders may include a number of such two bit adders in the signal path for a single bit. Thus, longer gate delays from printing the multiplier gate layer slightly out-of-focus is cumulative and, essentially, each two bit adder slows that signal path by the same amount with the overall result being the sum of the individual additional delay. By contrast simpler logic functions such as inverters or buffers may be formed with less dense or even isolated gates. A typical clock tree may be a series of such inverters and, as with the multiplier, the effect of printing the isolated clock tree gates is cumulative, shortening the delays by the sum of individual reductions. For timing critical applications, e.g., where the clock is gating a latch at the multiplier output, the later arrival of the multiplier results and earlier arrival of the clock can cause the latch to latch wrong data.
Thus, there is a need for reduced improved immunity to fabrication parameter variations in integrated circuit chip circuits.